1. Field of the Invention
The present invention relates to: a behavioral synthesis apparatus of a computer system for performing a computer-automated synthesis of a circuit description of a register transfer level (RTL) from a behavioral description (design specification of a circuit) having a circuit behavior described therein in order to support designing and manufacturing of a digital circuit; a behavioral synthesis method using the behavioral synthesis apparatus; a method for manufacturing the digital circuit using the behavioral synthesis apparatus; a behavioral synthesis control program for performing the behavioral synthesis method; and a computer-readable recording medium having the behavioral synthesis control program recorded thereon.
2. Description of the Related Art
For example, in designing a large scale integrated circuit (e.g., system LSI), a behavioral synthesis process is performed in order to automatically synthesize hardware of an RTL from a behavioral description of a circuit by using a computer system. This behavioral synthesis is also called a high-level synthesis.
A procedure of this behavioral synthesis process can be broadly classified into: data flow graph generation process; scheduling process; allocation process and the like.
The data flow graph generation process generates a data flow graph based on a behavioral description of a circuit, which only describes behaviors of the circuit but does not describe information regarding a structure of hardware. This data flow graph is also called “CDFG” (Control Data Flow Graph), where a flow of data is represented as a branch and each process (e.g., computation and communication) is represented as a node in a graph.
The scheduling process determines during which execution cycle each process (e.g., computation and communication) in the data flow graph should be executed.
The allocation process allocates a computation process to a circuit element (e.g., computing unit) and also allocates data being currently processed to a register for storage, for example.
Data path and a controller (control circuit) for controlling the data path are generated in accordance with the result of the scheduling process and the allocation process. As a result, hardware which behaves in the same manner as described by the behavioral description is obtained. In general, this obtained hardware is output as a circuit description of a register transfer level (RTL).
In a method for synthesizing hardware from the behavioral description, as one of conventional techniques for reducing power consumption of synthesized hardware, Reference 1 discloses the following. In this conventional technique, a circuit for controlling a clock is synthesized per blocks operating in parallel in hardware. The provision of the clock to the blocks in the circuit is stopped when the blocks are in a wait state in order to lower the power consumption of the hardware.
As another conventional technique for realizing low power consumption, Reference 2 is cited, which discloses “HIGH LEVEL SYNTHESIS METHOD AND APPARATUS”. In this conventional technique, a timing of a clock to be input to a register during scheduling is shifted, thereby reducing the number of registers in order to reduce power consumption.
[Reference 1] Japanese Laid-Open Publication No. 2002-366596
[Reference 2] Japanese Laid-Open Publication No. 2003-150657